The present invention relates to integrated circuits, and, more particularly, to an operational amplifier that operates at a low supply voltage and has a low offset voltage.
For an operational amplifier, low supply voltage refers to a voltage of around 1.8 V. This voltage corresponds to the voltage of two series connected batteries with a nominal voltage of 1.5 volts in a discharged state. In the discharged state, these batteries each have a voltage of around 0.9 volts. An amplifier capable of functioning with a voltage greater than or equal to 1.8 volts optimizes the energy available in battery powered devices. The use of such an amplifier, however, is not limited to battery powered devices.
Operational amplifiers are in various types of electronic circuits, and, in particular, circuits requiring a high current gain. An operational amplifier may be used in interface circuits, power stages, adding circuits, filters, etc. Moreover, operational amplifiers are particularly used in portable devices, such as headphones or mobile telephones, regardless of whether they are being powered by batteries. Moreover, operational amplifiers are particularly used in portable devices, such as headphones or mobile telephones, regardless of whether they are being powered by batteries.
An operational amplifier in accordance with the prior art is illustrated in FIG. 1. The amplifier has an input stage 100 with first and second input arms 102a, 102b, which form a differential pair of input arms. The input arms 102a, 102b each have an input transistor 104a, 104b respectively connected to input resistors 106a, 106b. Each input resistor 106a and 106b is respectively connected between a first supply terminal 1 and the collector of the corresponding input transistor 104a, 104b. In addition, the emitters of the input transistors are connected in common to a second supply terminal 22 by a biasing current source 108.
In the example in FIG. 1, the input transistors 104a, 104b are of the pnp type, and the first and second supply terminals 1, 2 are respectively a ground terminal and a supply terminal that is at a positive potential with respect to ground. The transistors 104a, 104b have substantially the same characteristics. The bases of the transistors 104a, 104b form input terminals 100a, 110b of the operational amplifier. A signal can be applied to the amplifier in the form of a potential difference between the input terminals 110a and 110b, thus forming a differential input. The potential difference applied between the input terminals has the effect of causing a differential current to flow in the input arms 102a and 102b. This is defined with respect to an idle state in which no voltage is applied to the input.
A second stage 200 of the amplifier is a level-transforming stage. It has first and second transforming arms 202a, 202b connected respectively to nodes 103a, 103b of the input stage. The nodes 103a and 103b are situated respectively between the input transistors and the input resistors of the first and second input arms 102a, 102b. The function of the level-transforming stages is to increase the voltage available at the nodes 103a and 103b so that the input resistors may drive a gain stage with sufficient voltage.
Each transforming arm has respective transistor 204a, 204b. The bases of these transistors are connected together by a node 205 so that they are commonly set to the same potential. The characteristics of the transistors 204a and 204b are substantially identical.
In the illustrated example, the transistors 204a, 204b of the first and second transforming arms are of the npn type and have emitters connected respectively to the nodes 103a, 103b of the input stage. The collectors of the transistors 204a, 204b are connected to the second supply terminal 2 by respective current sources 208a, 208b.
The transforming stage 200 also has a centering arm comprising a centering transistor 207 in series with a centering current source 209 between the first and second supply terminals. The centering current source 209 connects to the first supply terminal 1 the node 205 between the bases of the transistors 204a and 204b in the transforming arms.
In addition, the centering transistor has a collector connected to the second supply terminal 2, an emitter connected to the node 205 between the bases of the transistors 202a, 202b, and a base connected to the collector 203a of the transistor 204a in the first transforming arm 202a. The role of the centering arm is discussed in greater detail below.
A third stage of the amplifier is indicated with reference 300. This is a current gain stage which connects the level-transforming stage 200 to an output terminal 302.
A plurality of gain stages can be provided between the level-transforming stage 200 and the output terminal 302. In this case, the plurality of gain stages forms a gain chain. The input of the gain stage is represented by a transistor 304 whose base is connected to the collector 203b of the transistor 204b in the second transforming arm 202b. The transistor 304 is an npn bipolar type. Its emitter is connected to the first supply terminal 1 and its collector is connected to the second supply terminal 2 by a biasing current source 308.
The functioning of the amplifier of FIG. 1 is briefly described below. Considering that the input resistors 106a, 106b have identical values denoted Re, and considering that the transistors 204a and 204b in the transforming arms 202a and 202b have the same transconductance denoted gm, it is possible to write:       Δ    ⁢          xe2x80x83        ⁢          I      s        =                              g          m                ⁢                  R          E                            1        +                              g            m                    ⁢                      R            E                                ⁢    Δ    ⁢          xe2x80x83        ⁢          I      E      
In this equation xcex94Is indicates a total variation in the current conducted via the transistors in the input arms in response to a potential difference applied between the input terminals 110a and 110b. xcex94IE is the variation in the base current of the transistor 304 of the gain stage which results therefrom.
The value of gm is such that, where       g    m    =                    qI        208            kT        .  
The variable I208 is the (identical) value of the biasing currents delivered respectively by the biasing sources 208a, 208b in the transforming arms 202a, 202b, k is Boltzmann""s constant, q is the electron charge and T is the temperature.
In the case of an ideal amplifier, the output voltage measured between the supply terminal 1 and the output terminal 302 would become zero when no potential difference is applied between the input terminals 110a, 110b. However, this is generally not the case because all the components used for building the amplifier, and in particular, the components of the symmetrical arms of the stages, have a variation in their characteristics. This means that the output voltage of the amplifier is not zero in the absence of an input voltage. The state in which no input voltage is applied to the input of the amplifier is also referred to as an idle state in the remainder of the text.
Thus, an offset voltage is defined as being the voltage which must be applied between the input terminals 110a, 110b so that the output voltage of the amplifier available between the supply terminal 1 and the output terminal 302 is zero. A zero output voltage in the gain stage or gain stages is obtained when the base current, when idle in the transistor 304 at the input of the gain stage, has a given value denoted IE. The value IE depends on the characteristic of the gain stage or stages.
It is required that the offset voltage should be as low as possible, and preferably zero. As a first approximation, the offset voltage is zero if the currents in the transistors 104a and 104b in the input arms are identical to each other when idle, and if the currents in the transistor 204a, 204b in the transforming arms are identical to each other.
This is the case if the current supplied by the current sources 208a and 208b are also identical to each other, and the current taken from the collector 203a of the transistor 204a in the first transforming arm 202a is equal to the current taken at the collector 203b of the transistor 204b in the second transforming arm 202b. In other words, it is necessary that, when idle, the base current of the transistor 207 in the compensation arm corresponds substantially to the input current of the gain stage 300.
The base current of the transistor 207 can be controlled by adjusting the current delivered by the current source 209 in the compensation arm. The current delivered by the current source 209 is consequently adjusted so that the offset voltage is substantially zero. When the transistor 207 in the compensation arm has characteristics substantially identical to those of the input transistor 304 in the gain stage 300, and, in particular, the same current gain, the current delivered by the current source 209 of the compensation arm is adjusted to be substantially equal to the emitter current of the transistor 304 in the gain stage.
The functioning of an amplifier according to the diagram in FIG. 1 does, however, has limits when the voltage available between the first and second supply terminals is low. In particular, transistors (not shown) used in the biasing current sources 208a, 208b may be saturated when the supply voltage is too low. By way of illustration, the base voltage of the transistor 207 in the compensation arm, that is, the voltage VB at node 203a, is such that:
Vb=VBE204a+VBE207+R106a*(208+I104a)
In this expression VBE204a, VBE207, R106a, I208 and I104a designate respectively the base-emitter voltage of the transistor 204a in the first transforming arm 202a, the base-emitter voltage of the transistor 207 in the compensation arm, the value of the resistor 106a in the first input arm, the current supplied by the biasing current source 208a in the first transforming arm, and the current passing through the input transistor 104a in the first input arm 102a. The base-emitter voltages of the bipolar transistors are such that VBZ204a≈VBE207≈0.75 V. In addition, a value commonly adopted for the term R106a≈(I208+I104a) is on the order of 0.15 V. Lower voltages would be inappropriate for driving the following stages. Thus VB ≈1.650 V.
When the voltage VCC at the supply terminals is as low as VCC=1.8 volts, the remaining voltage available for the biasing current source 208a in the first transforming arm is only 150 mV. In so far as the current source comprises a bipolar transistor, and a pnp type transistor, a voltage of around 150 mV between its emitter and collector terminals is close to a saturation value. To avoid the risk of saturation, it is therefore necessary to have a higher supply voltage which cannot attain values as low as 1.8 V.
FIG. 2 depicts a variation of the circuit in FIG. 1. This variation is one approach to the problem discussed above, but does not, however, prove entirely satisfactory. For reasons of convenience, parts of FIG. 2 which are identical, similar or equivalent to those of FIG. 1 are marked with the same references.
The diagram in FIG. 2 is identical to that of FIG. 1 with the exception of the compensation arm. This is replaced by a bypass arm 201 which connects the collector and base of the transistor 204a in the first transforming arm 202a. In other words, the bypass arm 201 connects node 203a to node 205.
By designating as I208 as the biasing current delivered respectively by each current source 208a, 208b in the transforming stage 200, the base current of the transistors 204a, 204b is equal as a first approximation to             I      208        β    ,
where xcex2 is the current gain of these transistors. The diversion branch 201 consequently has passing through it a current substantially equal to             2      ⁢              I        208              β    .
In an amplifier in accordance with the diagram in FIG. 2, a centering of the offset voltage to a substantially zero value is accomplished when the bypass currents in each of the transforming branches 202a, 202b are balanced. Thus, the idle current entering the gain stage 300, that is, the base current of the input transistor 304 of this stage, must be substantially equal to the current passing through the diversion branch 201. The current is equal to             2      ⁢              I        208              β    .
Since the input transistor 304 has a current gain substantially equal to the gain xcex2 of the transistors in the transforming stage 200, the biasing current source 308 of the gain stage supplies a current I305 such that I305≈2I208. Thus, for an amplifier in accordance with FIG. 2, the biasing currents cannot be chosen freely, but are chosen so that the biasing current I208 of each of the transforming arms is a function of the gain stage current.
In the example illustrated,       I          208      ⁢      a        =            I              208        ⁢        b              =                  I        308            2      
with I208a=I208b=I208, and I208a I208b are respective currents in the first and second transforming arms. This link between the currents in the different arms form an important constraint in setting up the amplifier, and restricts its field of use. This is because the biasing current I209 of the gain stage is generally fixed according to the performance required for the amplifier, such as, for example, certain dynamic behavior or the maximum value of the output current. Thus, in general, a biasing current I309 of high value is sought.
However, the biasing currents in the transforming arms influence other parameters, such as the speed of operation, noise, and variations in the offset voltage, etc. For these parameters it may be necessary to choose biasing currents lower than             I      308        2    .
When the biasing currents in the transforming arms and the biasing current in the gain stage are linked, it is no longer possible to independently optimize the different operating parameters mentioned above. The choice of the biasing currents then necessarily results from a compromise between the different parameters.
By way of example, a high current value I308 is desirable so that the amplifier can deliver high output currents. This choice necessitates also high values of the currents I208a and I208b. However, high biasing currents for the transforming stage makes the amplifier sensitive with regards to its offset voltage, and to a variation in the characteristics of the components of the first and second transforming arms 202a and 202b.
Conversely, low biasing currents limit the output current of the amplifier. This is not desirable when the supply voltage available is also low. Thus, the approach disclosed in accordance with FIG. 2 would not be satisfactory.
In view of the foregoing, it is therefore an object of the present invention to provide an operational amplifier which permits the independent setting of the biasing currents of each stage, and thus to enable optimization of the different operating parameters of the amplifier.
Another object of the present invention is to provide an amplifier capable of functioning with low supply voltages as low as 1.8 volts without saturating the transistors therein.
Yet another object of the present invention is to provide an amplifier having a low idle current and a low idle consumption.
These and other objects, features and advantages in accordance with the present invention are provided by an operational amplifier comprising an input stage with first and second input arms forming a differential pair, and a level-transforming stage with first and second transforming arms each having at least one bipolar transistor. The bipolar transistors in the first and second transforming arms are respectively connected to the first and second input arms, and are connected together mutually by their bases. At least one gain stage is connected to the transistor in the second transforming arm.
In accordance with the present invention, a current terminal of the transistor in the first transforming arm is connected to the base of the transistor by a bypass arm. In addition, the amplifier has a centering arm that includes a centering transistor in series with a centering resistor. The centering transistor is connected by its base to those of the transistors in the transforming arms for controlling a current flowing in the bypass arm.
The current terminal of a transistor refers to a terminal through which the principal current of the transistor passes. In the case of a bipolar transistor, it is either the emitter terminal or the collector terminal. Biasing of the different arms, and, in particular, the transforming arms, may be accomplished using bipolar transistors.
However, by virtue of the characteristics of the present invention, the voltage available for biasing is greater than that existing in the circuits of the prior art. It therefore makes it possible to prevent saturation of the transistors thereof. This also includes the other transistors in the amplifier. The amplifier can thus be powered at supply voltages as low as 1.8 volts. Moreover, the values of the idle currents can be set independently for each of the stages of the amplifier. These aspects will be examined more precisely below in the description.
According to one embodiment of the amplifier, the transistors in the branches of the transforming stage may be chosen so that they are substantially identical. In this case, the value of the centering resistor is preferably chosen to set in the bypass arm a current equal to the input current of the gain stage. This choice of the centering resistor makes it possible to cancel out the offset voltage, or at least to make it as low as possible.
According to another embodiment of the amplifier, the transistors in the transforming branches may be an npn type, with an emitter terminal connected to one of the input arms and a collector terminal connected to a supply terminal by a biasing circuit. In this case, the collector of the transistor in the first transforming arm is connected to the base of the transistor by the bypass arm.